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FEATURES 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Guaranteed Monotonic (TMIN to T MAX) Space-Saving 0.3" DIPs and 24- or 28-Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc. Low Power LC 2MOS APPLICATIONS Automatic Test Equipment Digital Attenuators Programmable Power Supplies Programmable Gain Amplifiers Digital-to-4-20 mA Converters
LC2MOS Complete 12-Bit Multiplying DAC AD7845
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7845 is the industry's first 4-quadrant multiplying D/A converter with an on-chip amplifier. It is fabricated on the LC2MOS process, which allows precision linear components and digital circuitry to be implemented on the same chip. The 12 data inputs drive latches which are controlled by standard CS and WR signals, making microprocessor interfacing simple. For stand-alone operation, the CS and WR inputs can be tied to ground, making all latches transparent. All digital inputs are TTL and 5 V CMOS compatible. The output amplifier can supply 10 V into a 2 k load. It is internally compensated, and its input offset voltage is low due to laser trimming at wafer level. For normal operation, RFB is tied to VOUT, but the user may alternatively choose RA, RB or RC to scale the output voltage range.
1. Voltage Output Multiplying DAC The AD7845 is the first DAC which has a full 4-quadrant multiplying capability and an output amplifier on chip. All specifications include amplifier performance. 2. Matched Application Resistors Three application resistors provide an easy facility for gain ranging, voltage offsetting, etc. 3. Space Saving The AD7845 saves space in two ways. The integration of the output amplifier on chip means that chip count is reduced. The part is housed in skinny 24-lead 0.3" DIP, 28-terminal LCC and PLCC and 24-terminal SOIC packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD7845-SPECIFICATIONS1 (V T= +15 TV, V connected to R . V load = 2 k , 100 pF. All specifications to
DD OUT FB OUT MIN
5%, VSS = -15 V,
S Version 12 1 1 1 2 4 5 3 6 6 7 2
5%, VREF = +10 V, AGND = DGND = O V,
Units Bits LSB max LSB max LSB max mV max mV max V/C typ LSB max LSB max LSB max LSB max Test Conditions/Comments 1 LSB =
MAX unless otherwise noted.)
Parameter ACCURACY Resolution Relative Accuracy at +25C TMIN to T MAX Differential Nonlinearity Zero Code Offset Error at +25C TMIN to T MAX Offset Temperature Coefficient; (Offset/Temperature) 2 Gain Error
J Version 12 1 1 1 2 3 5 3 6 6 7
K Version 12 1/2 3/4 1 1 2 5 2 6 6 7 2
A Version 12 1 1 1 2 3 5 3 6 6 7 2
B Version 12 1/2 3/4 1 1 2 5 2 6 6 7 2
T Version 12 1/2 3/4 1 1 3 5 2 6 6 7 2
VREF 212
= 2.4 mV
All Grades Are Guaranteed Monotonic over Temperature DAC Register Loaded with All 0s.
RFB, VOUT Connected RC, VOUT Connected, VREF = +5 V RB, VOUT Connected, VREF = +5 V RA, VOUT Connected, VREF = +2.5 V
Gain Temperature Coefficient; 2 (Gain/Temperature) 2 REFERENCE INPUT Input Resistance, Pin 17 APPLICATION RESISTOR RATIO MATCHING DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) CIN (Input Capacitance) 2 POWER SUPPLY4 VDD Range VSS Range Power Supply Rejection Gain/VDD Gain/VSS IDD ISS
ppm of FSR/C RFB, VOUT Connected typ k min k max % max V min V max A max pF max V min/V max V min/V max % per % max % per % max mA max mA max VDD = +15 V 5%, VREF = -10 V VSS = -15 V 5%. VOUT Unloaded VOUT Unloaded Typical Input Resistance = 12 k
8 16 0.5 2.4 0.8 1 7
8 16 0.5 2.4 0.8 1 7
8 16 0.5 2.4 0.8 1 7
8 16 0.5 2.4 0.8 1 7
8 16 0.5 2.4 0.8 1 7
8 16 05 2.4 0.8 1 7
Matching Between RA, RB, RC
Digital Inputs at 0 V and V DD
14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 -14.25/-15.75 -14.25/-15.75 -14.25/-15.75 -14.25/-15.75 0.01 0.01 6 4 0.01 0.01 6 4 0.01 0.01 6 4 0.01 0.01 6 4
14.25/15.75 14.25/15.75 -14.25/-15.75 -14.25/-15.75 0.01 0.01 6 4 0.01 0.01 6 4
AC PERFORMANCE CHARACTERISTICS
DYNAMIC PERFORMANCE Output Voltage Settling Time 5 5 5
These characteristics are included for Design Guidance and are not subject to test.
5 5 5 s max To 0.01% of Full-Scale Range VOUT Load = 2 k, 100 pF. DAC Register Alternately Loaded with All 0s and All 1s. Typically 2.5 s at 25C. VOUT Load = 2 k, 100 pF. Measured with V REF = 0 V. DAC Register Alternately Loaded with All 0s and All 1s. VREF = 10 V, 10 kHz Sine Wave DAC Register Loaded with All 0s. VOUT, RFB Connected. DAC Loaded with All 1s VREF = 100 mV p-p Sine Wave. VOUT, RFB Connected. DAC Loaded with All 1s. VREF = 20 V p-p Sine Wave. R L = 2 k. VREF = 6 V rms, 1 kHz Sine Wave. VOUT, RFB Not Connected VOUT = 10 V, RL = 2 k RL = 2 k, CL = 100 pF RFB, VOUT Connected, VOUT Shorted to AGND Includes Noise Due to Output Amplifier and Johnson Noise of RFB
Slew Rate Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error3 Unity Gain Small Signal Bandwidth
11 55
11 55
11 55
11 55
11 55
11 55
V/s typ nV-s typ
5
5
5
5
5
5
mV p-p typ
600
600
600
600
600
600
kHz typ
Full Power Bandwidth
175
175
175
175
175
175
kHz typ
Total Harmonic Distortion
-90
-90 85 10 0.2 11 2 250 100 50 50 50
-90 85 10 0.2 11 2 250 100 50 50 50
-90 85 10 0.2 11 2 250 100 50 50 50
-90 85 10 0.2 11 2 250 100 50 50 50
-90 85 10 0.2 11 2 250 100 50 50 50
dB typ dB min V min typ mA typ V rms typ nV/Hz typ nV/Hz typ nV/Hz typ nV/Hz typ nV/Hz typ
OUTPUT CHARACTERISTICS5 Open Loop Gain 85 Output Voltage Swing Output Resistance Short Circuit Current @ +25C Output Noise Voltage (0.1 Hz to 10 Hz) @ +25C f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 100 kHz 10 0.2 11 2 250 100 50 50 50
NOTES 1Temperature ranges are as follows: J, K Versions: 0C to +70C; A, B Versions: -40C to +85C; S, T Versions: -55C to +125C. 2Guaranteed by design and characterization, not production tested. 3The metal lid on the ceramic D-24A package is connected to Pin 12 (DGND). 4The device is functional with a power supply of 12 V. 5Minimum specified load resistance is 2 k. Specifications subject to change without notice.
-2-
REV. B
AD7845 TIMING CHARACTERISTICS1 (V
Parameter tCS tCH tWR tDS tDH 30 0 30 80 0
DD
= +15 V,
5%. VSS = -15 V,
Units ns min ns min ns min ns min ns min
5%. VREF = +10 V. AGND = DGND = O V.)
Test Conditions/Comments Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulsewidth Data Setup Time Data Hold Time
Limit at TMIN to TMAX (All Versions)
NOTES 1 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +17 V VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to -17 V VREF to AGND . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS - 0.3 V VRFB to AGND . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS - 0.3 V VRA to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS - 0.3 V VRB to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS - 0.3 V VRC to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS - 0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . VDD + 0.3 V, VSS - 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V Power Dissipation (Any Package) To +75C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW Derates above +75C . . . . . . . . . . . . . . . . . . . . . 10 mW/C
Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . 0C to +70C Industrial (A, B Versions) . . . . . . . . . . . . -40C to +85C Extended (S, T Versions) . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. 2 VOUT may be shorted to AGND provided that the power dissipation of the package is not exceeded.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7845 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE1
WARNING!
ESD SENSITIVE DEVICE
Model2 AD7845JN AD7845KN AD7845JP AD7845KP AD7845JR AD7845KR AD7845AQ AD7845BQ AD7845AR AD7845BR AD7845SQ/883B AD7845TQ/883B AD7845SE/883B
Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C
Relative Accuracy @ +25 C 1 LSB 1/2 LSB 1 LSB 1/2 LSB 1 LSB 1/2 LSB 1 LSB 1/2 LSB 1 LSB 1/2 LSB 1 LSB 1/2 LSB 1 LSB
tCS
tCH
5V
Package Option3 N-24 N-24 P-28A P-28A R-24 R-24 Q-24 Q-24 R-24 R-24 Q-24 Q-24 E-28A
CS 0V tWR 5V WR 0V tDS tDH 5V DATA 0V NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. tR = tF = 20ns. V +V 2. TIMING MEASUREMENT REFERENCE LEVEL IS IH 2 IL
Figure 1. AD7845 Timing Diagram
NOTES 1Analog Devices reserves the right to ship either ceramic (D-24A) or cerdip (Q-24) hermetic packages. 2To order MIL-STD-883, Class B processed parts, add /883B to part number. 3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
REV. B
-3-
AD7845
PIN CONFIGURATIONS DIP, SOIC LCC PLCC
TERMINOLOGY
LEAST SIGNIFICANT BIT DIGITAL-TO-ANALOG GLITCH IMPULSE
This is the analog weighting of 1 bit of the digital word in a V REF DAC. For the AD7845, 1 LSB = 12 . 2
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for both endpoints (i.e., offset and gain error are adjusted out) and is normally expressed in least significant bits or as a percentage of full-scale range.
DIFFERENTIAL NONLINEARITY
This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage. The measurement takes place with VREF = AGND.
DIGITAL FEEDTHROUGH
When the DAC is not selected (i.e., CS is high) high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough.
MULTIPLYING FEEDTHROUGH ERROR
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of +1 LSB max over the operating temperature range ensures monotonicity.
GAIN ERROR
This is ac error due to capacitive feedthrough from the VREF terminal to VOUT when the DAC is loaded with all 0s.
OPEN-LOOP GAIN
Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Gain error is adjustable to zero with an external potentiometer. See Figure 13.
ZERO CODE OFFSET ERROR
Open-loop gain is defined as the ratio of a change of output voltage to the voltage applied at the VREF pin with all 1s loaded in the DAC. It is specified at dc.
UNITY GAIN SMALL SIGNAL BANDWIDTH
This is the error present at the device output with all 0s loaded in the DAC. It is due to the op amp input offset voltage and bias current and the DAC leakage current.
TOTAL HARMONIC DISTORTION
This is the frequency at which the magnitude of the small signal voltage gain of the output amplifier is 3 dB below unity. The device is operated as a closed-loop unity gain inverter (i.e., DAC is loaded with all 1s).
OUTPUT RESISTANCE
This is the effective output source resistance.
FULL POWER BANDWIDTH
This is the ratio of the root-mean-square (rms) sum of the harmonics to the fundamental, expressed in dBs.
OUTPUT NOISE
This is the noise due to the white noise of the DAC and the input noise of the amplifier. -4-
Full power bandwidth is specified as the maximum frequency, at unity closed-loop gain, for which a sinusoidal input signal will produce full output at rated load without exceeding a distortion level of 3%.
REV. B
Typical Performance Characteristics-AD7845
Figure 2. Frequency Response, G = -1
Figure 3. Output Voltage Swing vs. Resistive Load
Figure 4. Noise Spectral Density
Figure 5. THD vs. Frequency
Figure 6. Typical AD7845 Linearity vs. Power Supply
Figure 7. Multiplying Feedthrough Error vs. Frequency
80 70 60 50 OUTPUT - mV 40 30 20 10 0 -10 -20 0 2 4 6 8 10 12 14 16 TIME - s 18 20
Figure 8. Unity Gain Inverter Pulse Response (Large Signal)
Figure 9. Unity Gain Inverter Pulse Response (Small Signal)
Figure 10. Digital-to-Analog Glitch Impulse (All 1s to All 0s Transition)
REV. B
-5-
AD7845
PIN FUNCTION DESCRIPTION (DIP)
Pin 1 2-11 12 13-14 15 16 17 18 19 20 21 22 23 24
Mnemonic VOUT DB11-DB2 DGND DB1-DB0 WR CS VREF AGND VSS VDD RA RB RC RFB
Description Voltage Output Terminal Data Bit 11 (MSB) to Data Bit 2 Digital Ground. The metal lid on the ceramic package is connected to this pin Data Bit 1 to Data Bit 0 (LSB) Write Input. Active low Chip Select Input. Active low Reference Input Voltage which can be an ac or dc signal Analog Ground. This is the reference point for external analog circuitry Negative power supply for the output amplifier (nominal -12 V to +15 V) Positive power supply (nominal +12 V to +15 V) Application resistor. RA = 4 RFB Application resistor. RB = 2 RFB Application resistor. RC = 2 RFB Feedback resistor in the DAC. For normal operation this is connected to VOUT
CIRCUIT INFORMATION Digital Section
Each of the switches A-C steers 1/4 of the total reference current with the remaining 1/4 passing through the R-2R section. An output amplifier and feedback resistor perform the currentto-voltage conversion giving VOUT = - D x VREF where D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.) The amplifier can maintain 10 V across a 2 k load. It is internally compensated and settles to 0.01% FSR (1/2 LSB) in less than 5 s. The input offset voltage is laser trimmed at wafer level. The amplifier slew rate is typically 11 V/s, and the unity gain small signal bandwidth is 600 kHz. There are three extra on-chip resistors (RA, R B, RC ) connected to the amplifier inverting terminal. These are useful in a number of applications including offset adjustment and gain ranging.
VREF R R 2R S9 2R S8 R 2R S0 IOUT AGND 2R
Figure 11 is a simplified circuit diagram of the AD7845 input control logic. When CS and WR are both low, the DAC latch is loaded with the data on the data inputs. All the digital inputs are TTL, HCMOS and +5 V CMOS compatible, facilitating easy microprocessor interfacing. All digital inputs incorporate standard protection circuitry.
Figure 11. AD7845 Input Control Logic
2R 2R B 2R A
D/A Section
C
Figure 12 shows a simplified circuit diagram for the AD7845 D/A section and output amplifier. A segmented scheme is used whereby the 2 MSBs of the 12-bit data word are decoded to drive the three switches A-C. The remaining 10 bits drive the switches (S0-S9) in a standard R-2R ladder configuration.
SHOWN FOR ALL 1s ON DAC
Figure 12. Simplified Circuit Diagram for the AD7845 D/A Section
-6-
REV. B
AD7845
UNIPOLAR BINARY OPERATION
Figure 13 shows the AD7845 connected for unipolar binary operation. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. The code table for Figure 13 is given in Table I.
BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
The recommended circuit for bipolar operation is shown in Figure 14. Offset binary coding is used. The offset specification of this circuit is determined by the matching of internal resistors RB and RC and by the zero code offset error of the device. Gain error may be adjusted by varying the ratio of R1 and R2. To use this circuit without trimming and keep within the gain error specifications, resistors R1 and R2 should be ratio matched to 0.01%. The code table for Figure 14 is given in Table II.
Figure 13. Unipolar Binary Operation
Table I. Unipolar Binary Code Table for AD7845
Binary Number In DAC Register MSB 1111 1111 LSB 1111
Analog Output, VOUT 4095 -VIN 4096 2048 -VIN = -1/2 VIN 4096 1 -VIN 4096 0V
1000
0000
0000
Figure 14. Bipolar Offset Binary Operation
Table II. Bipolar Code Table for Offset Binary Circuit of Figure 14
0000 0000
0000 0000
0001 0000
Binary Number In DAC Register MSB 1111 1111 LSB 1111
Analog Output, VOUT 2047 +V IN 2048 1 +V IN 2048 0V 1 -VIN 2048 2048 -VIN 2048 = -VIN
OFFSET AND GAIN ADJUSTMENT FOR FIGURE 13 Zero Offset Adjustment
1. Load DAC with all 0s. 2. Trim R3 until VOUT = 0 V.
Gain Adjustment
1000 4095 . 4096 1000 0111
0000 0000 1111
0001 0000 1111
1. Load DAC with all 1s. 2. Trim R1 so that VOUT = -VIN
In fixed reference applications, full scale can also be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude. For high temperature applications, resistors and potentiometers should have a low temperature coefficient.
0000
0000
0000
REV. B
-7-
AD7845
APPLICATIONS CIRCUITS PROGRAMMABLE GAIN AMPLIFIER (PGA) PROGRAMMABLE CURRENT SOURCES
The AD7845 performs a PGA function when connected as in Figure 15. In this configuration, the R-2R ladder is connected in the amplifier feedback loop. RFB is the amplifier input resistor. As the code decreases, the R-2R ladder resistance increases and so the gain increases. VOUT = -VIN x 1 4095 RDAC x , D = 0 to RFB 4096 D
The AD7845 is ideal for designing programmable current sources using a minimum of external components. Figures 16 and 17 are examples. The circuit of Figure 16 drives a programmable current IL into a load referenced to a negative supply. Figure 17 shows the circuit for sinking a programmable current, IL. The same set of circuit equations apply for both diagrams. IL = I3 = I2 + I1 I1 = D x| IN | V , RDAC 4095 D = 0 to 4096
1 R -VIN = -VIN x DAC x = , since RFB = RDAC RDAC D D
I2 =
V 1 D x| IN | D x| IN | V R= , since RFB = RDAC R1 RDAC FB R1 V D x| IN | D x| IN | V + RDAC R1 D x| IN | V x R1 R1 1 + RDAC
IL =
=
Note that by making R1 much smaller than RDAC, the circuit becomes insensitive to both the absolute value of RDAC and its temperature variations. Now, the only resistor determining load current IL is the sense resistor R1. If R1 = 100 , then the programming range is 0 mA to 100 mA, and the resolution is 0.024 mA.
Figure 15. AD7845 Connected as PGA
As the programmed gain increases, the error and noise also increase. For this reason, the maximum gain should be limited to 256. Table III shows gain versus code. Note that instead of using RFB as the input resistor, it is also possible to use combinations of the other application resistors, RA, R B and RC. For instance, if RB is used instead of RFB , the gain range for the same codes of Table II now goes from l/2 to 128.
Table III. Gain and Error vs. Input Code for Figure 15
Digital Inputs 1111 1000 0100 0010 0001 0000 0000 0000 0000 1111 0000 0000 0000 0000 1000 0100 0010 0001 1111 0000 0000 0000 0000 0000 0000 0000 0000
Gain 4096/4095 1 2 4 8 16 32 64 128 256
Error (%) 0.04 0.07 0.13 0.26 0.51 1.02 2.0 4.0 8.0
Figure 16. Programmable Current Source
-8-
REV. B
AD7845
Figure 17. Programmable Current Sink
4-20 mA CURRENT LOOP
Figure 18. 4-20 mA Current Loop
APPLICATION HINTS
The AD7845 provides an excellent way of making a 4-20 mA current loop circuit. This is basically a variation of the circuits in Figures 16 and 17 and is shown in Figure 18. The application resistor RA (Value 4R) produces the effective 4 mA offset. IL = I3 = I2 + I1 Since I2 > I1, IL = - 2.5 2.5 VX x D x RFB x 1 = 4R x RFB + R DAC 156 156 and since RDAC=RFB=R 2.5 1000 IL = 4 + D x 2.5 x 156 mA = [4 + (16 x D)]mA, where D goes from 0 to 1 with Digital Code When D = 0 (Code of all 0s): IL = 4 mA When D = 1 (Code of all 1s): IL = 20 mA The above circuit succeeds in significantly reducing the circuit component count. Both the on-chip output amplifier and the application resistor RA contribute to this.
General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7845. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7845 AGND and DGND pins (IN914 or equivalent). Digital Glitches: When a new digital word is written into the DAC, it results in a change of voltage applied to some of the DAC switch gates. This voltage change is coupled across the switch stray capacitance and appears as an impulse on the current output bus of the DAC. In the AD7845, impulses on this bus are converted to a voltage by RFB and the output amplifier. The output voltage glitch energy is specified as the area of the resulting spike in nV-seconds. It is measured with VREF connected to analog ground and for a zero to full-scale input code transition. Since microprocessor based systems generally have noisy grounds which couple into the power supplies, the AD7845 VDD and VSS terminals should be decoupled to signal ground. Temperature Coefficients: The gain temperature coefficient of the AD7845 has a maximum value of 5 ppm/C. This corresponds to worst case gain shift of 2 LSBs over a 100C temperature range. When trim resistors R1 and R2 in Figure 13 are used to adjust full-scale range, the temperature coefficient of R1 and R2 must be taken into account. The offset temperature coefficient is 5 ppm of FSR/C maximum. This corresponds to a worst case offset shift of 2 LSBs over a 100C temperature range. The reader is referred to Analog Devices Application Note "Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs," Publication Number E630C-5-3/86.
REV. B
-9-
AD7845
MICROPROCESSOR INTERFACING 16-BIT MICROPROCESSOR SYSTEMS 8-BIT MICROPROCESSOR SYSTEMS
Figures 19, 20 and 21 show how the AD7845 interfaces to three popular 16-bit microprocessor systems. These are the MC68000, 8086 and the TM32010. The AD7845 is treated as a memory-mapped peripheral to the processors. In each case, a write instruction loads the AD7845 with the appropriate data. The particular instructions used are as follows: MC68000: 8086: MOVE MOV
Figure 22 shows an interface circuit for the AD7845 to the 8085A 8-bit microprocessor. The software routine to load data to the device is given in Table IV. Note that the transfer of the 12 bits of data requires two write operations. The first of these loads the 4 MSBs into the 7475 latch. The second write operation loads the 8 LSBs plus the 4 MSBs (which are held by the latch) into the DAC.
TMS32010: OUT
Figure 22. 8085A Interface
Table IV. Subroutine Listing for Figure 22
Figure 19. AD7845 to MC68000 Interface
2000 LOAD DAC: LXI
MVI MOV INR MVI MOV
Figure 20. AD7845 to 8086 Interface
RET
The H,L register pair are loaded with latch address 3000. A,#"MS" Load the 4 MSBs of data into accumulator. M,A Transfer data from accumulator to latch. L Increment H,L pair to AD7845 address. A,#"LS" Load the 8 LSBs of data into accumulator. M,A Transfer data from accumulator to DAC. End of routine.
H,#3000
Figure 21. TMS32010
-10-
REV. B
AD7845
Figure 23 and 24 are the interface circuits for the Z80 and MC6809 microprocessors. Again, these use the same basic format as the 8085A interface.
DIGITAL FEEDTHROUGH
In the preceding interface configurations, most digital inputs to the AD7845 are directly connected to the microprocessor bus. Even when the device is not selected, these inputs will be constantly changing. The high frequency logic activity on the bus can feed through the DAC package capacitance to show up as noise on the analog output. To minimize this digital feedthrough isolate the DAC from the noise source. Figure 25 shows an interface circuit which uses this technique. All data inputs are latched from the busy by the CS signal. One may also use other means, such as peripheral interface devices, to reduce the digital feedthrough.
Figure 23. AD7845 to Z80 Interface
Figure 25. AD7845 Interface Circuit Using Latches to Minimize Digital Feedthrough
Figure 24. MC6809 Interface
REV. B
-11-
AD7845
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP (N-24)
28-Terminal Leadless Ceramic Chip Carrier (E-28A)
C1189b-1-9/99
24-Lead Cerdip (Q-24)
28-Terminal Plastic Leaded Chip Carrier (P-28A)
24-Lead Ceramic DIP (D-24A)
0.6141 (15.60) 0.5985 (15.20)
24-Lead SOIC (R-24)
24
13
0.2992 (7.60) 0.2914 (7.40)
1 12
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC
8 0 0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-12-
REV. B
PRINTED IN U.S.A.
0.4193 (10.65) 0.3937 (10.00)

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